PeterCxy/irqbalance
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Set default deepestcache to 2

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Been meaning to do this for a while.  By default having a deepestcache value of
ULONG_MAX causes irqbalance to always find the deepest cache level in a systems
which causes it on some systems to think that all cpus share a cache, and as
such, that no balancing is needed.  Rectify this such that the default deepest
cache level is defaulted to 2

Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
This commit is contained in:
Neil Horman 2014-01-27 07:08:32 -05:00
parent d9138c78c3
commit d9a2cf2297
2 changed files with 9 additions and 6 deletions
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13
irqbalance.1
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@ -80,12 +80,15 @@ example to ban irqs 43 and 44 from balancing, use the following command line:
.TP
.B --deepestcache=<integer>
This allows a user to specify the cache level at which irqbalance partitions
cache domains. Without specified, irqbalance searches the available deepest
cache. This can affect how irqbalance builds up the CPU tree. For example, on
a system where all the CPU cores being within the same L3 cache domain, one
can let irqbalance build up the CPU tree on L2 cache by using the following
command line:
cache domains. Specifying a deeper cache may allow a greater degree of
flexibility for irqbalance to assign irq affinity to achieve greater performance
increases, but setting a cache depth too large on some systems (specifically
where all cpus on a system share the deepest cache lavel), will cause irqbalance
to see balancing as unnesessecary.
.B irqbalance --deepestcache=2
.P
The default value for deepestcache is 2.
.TP
.B -l, --policyscript=<script>

2
irqbalance.c
View file

@ -50,7 +50,7 @@ int need_rescan;
unsigned int log_mask = TO_ALL;
enum hp_e hint_policy = HINT_POLICY_IGNORE;
unsigned long power_thresh = ULONG_MAX;
unsigned long deepest_cache = ULONG_MAX;
unsigned long deepest_cache = 2;
unsigned long long cycle_count = 0;
char *pidfile = NULL;
char *banscript = NULL;