7bc1244fbf
This originally surfaced as a bug in placing network interrupts. In
the case that this submitter observed, the NIC card was in NUMA domain
0, but each RSS interrupt was getting an affinity list for all CPUs in
the domain. The expected behavior is for a single cpu to be chosen when
attempting to fan out NIC interrupts. Due to other implementation
details of interrupt placement, this effectively caused all interrupt
mappings for this NIC to end up on CPU 0.
The bug turns out ot have been caused by Intel Cluster on Die breaking
an assumption in irqbalance about the design of the component hierarchy.
The CoD topology allows a CPU package to belong to more than one NUMA
node, which is not expected.
The RCA was that when the second NUMA node was wired up to the existing
physical package, it overwrote the mappings that were placed there by
the first.
This patch attempts to solve that problem by permitting a package to
have multiple NUMA nodes. The CPU component hierarchy is preserved, in
case other parts of the code depend upon walking it. When a CoD
topology is detected, the NUMA node -> CPU component mapping is moved
down a level, so that the nodes point to the first level where the
affinity becomes distinct. In practice, this has been observed to be
the LLC.
A quick illustration (now, with COD, it looks like this):
+-----------+
| NUMA Node |
| 0 |
+-----------+
|
| +-------+
\|/ / | CPU 0 |
+---------+ +-------+
| Cache 0 |
+---------+ +-------+
/ \ | CPU 1 |
+-----------+ +-------+
| Package 0 |
+-----------+ +-------+
\ / | CPU 2 |
+---------+ +-------+
| Cache 1 |
+---------+
^ \ +-------+
| | CPU 3 |
| +-------+
+-----------+
| NUMA Node |
| 1 |
+-----------+
Whereas, previously only NUMA Node 1 would end up pointing to package 0.
The topology should not be different on platforms that do not enable
CoD.
Signed-off-by: Krister Johansen <kjlx@templeofstupid.com>
81 lines
1.3 KiB
C
81 lines
1.3 KiB
C
#ifndef _INCLUDE_GUARD_TYPES_H
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#define _INCLUDE_GUARD_TYPES_H
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#include <glib.h>
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#include "cpumask.h"
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#define BALANCE_NONE 0
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#define BALANCE_PACKAGE 1
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#define BALANCE_CACHE 2
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#define BALANCE_CORE 3
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/*
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* IRQ Classes
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*/
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#define IRQ_NODEF -1
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#define IRQ_OTHER 0
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#define IRQ_LEGACY 1
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#define IRQ_SCSI 2
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#define IRQ_VIDEO 3
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#define IRQ_ETH 4
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#define IRQ_GBETH 5
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#define IRQ_10GBETH 6
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#define IRQ_VIRT_EVENT 7
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/*
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* IRQ Types
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*/
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#define IRQ_TYPE_LEGACY 0
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#define IRQ_TYPE_MSI 1
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#define IRQ_TYPE_MSIX 2
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#define IRQ_TYPE_VIRT_EVENT 3
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/*
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* IRQ Internal tracking flags
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*/
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#define IRQ_FLAG_BANNED 1
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enum obj_type_e {
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OBJ_TYPE_CPU,
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OBJ_TYPE_CACHE,
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OBJ_TYPE_PACKAGE,
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OBJ_TYPE_NODE
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};
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struct topo_obj {
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uint64_t load;
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uint64_t last_load;
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uint64_t irq_count;
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enum obj_type_e obj_type;
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int number;
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int powersave_mode;
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cpumask_t mask;
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GList *interrupts;
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struct topo_obj *parent;
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GList *children;
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GList *numa_nodes;
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GList **obj_type_list;
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};
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struct irq_info {
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int irq;
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int class;
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int type;
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int level;
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int flags;
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struct topo_obj *numa_node;
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cpumask_t cpumask;
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cpumask_t affinity_hint;
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int hint_policy;
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uint64_t irq_count;
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uint64_t last_irq_count;
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uint64_t load;
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int moved;
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struct topo_obj *assigned_obj;
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unsigned int warned;
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char *name;
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};
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#endif
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